Suresh Rajgopal. Spatial Entropy ; a Uniied Attribute to Model

This dissertation addresses the problem of capturing the dynamic communi cation in VLSI circuits There are several CAD problems where attributes that combine behavior and structure are needed or when function behavior is too complex and is best captured through some attribute in the implemen tation Examples include timing analysis logic synthesis dynamic power estimation and variable ordering for binary decision diagrams BDDs In such a situation using static attributes computed from the structure of the implementation is not always helpful Firstly they do not provide su cient usage information and secondly they tend to exhibit variances with imple mentations which is not desirable while capturing function behavior The contribution of this research is a new circuit attribute called spa tial entropy It models the dynamic communication e ort in the circuit by unifying the static structure and the dynamic data usage Quantitatively spatial entropy measures the switching energy in a physical CMOS imple mentation A minimumspatial entropy implementation is a minimumenergy implementation For the purposes of this dissertation we restrict our scope to combinational circuits We propose a simple procedure to estimate spatial entropy in a gate level circuit It is characterized in extensive detail and we describe why it is di cult to compute spatial entropy accurately We show how it can also be de ned at other levels of abstraction We illustrate applications of spatial entropy in BDD variable ordering a problem that has traditionally relied on static attribute based solutions We also show empirically that spatial entropy can track function behavior through implementations by using it to measure gate count complexity in boolean functions